proceedings of the Sagamore Computer Conference, August 20-23, 1974
edited by Tse-yun Feng.
Berlin ; New York
Springer-Verlag
1975
(vi, 433 pages) : illustrations
Lecture notes in computer science, 24.
On a class of scheduling algorithms for multiprocessors computing systems --; Scheduling unit-time tasks with limited resources --; Programmable radar signal processing using the RAP --; Analysis and design of a cost-effective associative processor for weather computations --; The implementation of APL on an associative processor --; A unified associative and von-neumann processor EGPP and EGPP-array --; Discriminating content addressable memories --; A fundamental theorem of asynchronous parallel computation --; The hyperplane method for an array computer --; Syntactic recognition of parallel processes in formally defined complexes of interacting digital systems --; A control structure for parallel processing --; Toward the design of a network manager for a distributed computer network --; The typeset-10 message exchange facility a case study in systemic design --; Optimal resource allocation and scheduling among parallel processes --; A recognizer and post-recognizer for optimizing execution times of programs --; Analytic and implementation considerations of two-facility sequencing in computer systems --; Computer models with constrained parallel processors --; Implementation of data manipulating functions on the staran associative processor --; Mixed mode arithmetic for STARAN --; Aapl: An array processing language --; The evolution of a parallel active tracking program --; Implementation of the AWACS passive tracking algorithms on a Goodyear STARAN --; Experiences with an operational associative processor --; Matrix computations on an associative processor --; Optimal searching algorithms for parallel-pipelined computers --; A new parallel algorithm for network flow problems --; Parallel processing by virtual instruction --; An approach to restructurable computer systems --; On programmable parallel data routing networks via cross-bar switches for multiple element computer architectures --; A reconfigurable parallel arithmetic unit --; Architectural considerations in interfacing a parallel processor to the air traffic control system --; An efficient implementation of conflict prediction in a parallel processor --; An associative processor architecture for air traffic control --; Application of an associative processor to aircraft tracking --; Analysis of parallel processing for air defense and air traffic control for Thailand.