Chapter 1. Demand and challenges for wafer level chip-scale analog and power packaging --;Chapter 2. Fan-in wafer-level chip scale package --;Chapter 3. Fan-out wafer-level chip scale package --;Chapter 4. Stackable wafer level chip scale package --;Chapter 5. Wafer-level discrete power Mosfet package design --;Chapter 6. Wafer-level packaging TSV/Stack die for integration of analog and power solution --;Chapter 7. Thermal management, design, analysis for WLCSP --;Chapter 8. Electrical and multi-physics simulation for aAnalog and pPower WLCSP --;Chapter 9. WLCSP assembly --;Chapter 10. WLCSP typical reliability and test.
Analog and Power Wafer Level Chip Scale Packaging presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability and modeling.