عنوان

Source-synchronous networks-on-chip :

130627821X

1461494052 (electronic bk.)

9781306278218

9781461494058 (electronic bk.)

9781461494041

dltt

Source-synchronous networks-on-chip :

[Book]

circuit and architectural interconnect modeling /

Ayan Mandal, Sunil P. Khatri, Rabi Mahapatra

1 online resource (xiii, 143 pages) :

illustrations (some color)

Includes bibliographical references and index

Clock Distribution for fast Networks-on-Chip -- Fast Network-on-Chip Design -- Fast On-Chip Data transfer using Sinusoid Signals -- Conclusion and Future Work

0

This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic. Describes novel methods for high-speed network-on-chip (NoC) design; Enables readers to understand NoC design from both circuit and architectural levels; Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC; Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art

Networks on a chip-- Design.

Circuits and Systems.

Electronics and Microelectronics, Instrumentation.

Engineering.

Processor Architectures.

TEC-- 009070

TEC008010

TJFC

Mandal, Ayan

Khatri, Sunil P.,1965-

Mahapatra, Rabi N.

Ohio Library and Information Network.

20150224074306.0

pn

[Book]

Y