IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems : proceedings : 25-27 October 2000; Yamanshi, Japan
Sponsored by The IEEE computer society [and]& The IEEE computer society technical committee on fault-tolerant computing [and]& The computer society test technology technical committee
In cooperation with Technical group on fault tolerant systems, IEICE, Japan
Los Alamitos
IEEE Computer Society Press
2002
xii, 422 p. ill.
Includes bibliographic references and author index.
Integrated circuitsVery large scale integrationDesign and constructionCongresses
Fault-tolerant computingCongresses
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IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems\ 25-27 October 2000: Yamanashi, Japan